1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of fabricating shallow trench isolation (STI) structures.
2. Description of the Related Art
A device isolation structure is designed for preventing carrier movement between adjacent devices. Typically, device isolation regions are formed in ICs with high density. For example, device isolation regions can be formed between two adjacent field effect transistors (FET) in a dynamic random access memory (DRAM) to avoid leakage current. One of the common used methods for forming device isolation regions is local oxidation (LOCOS). The LOCOS technique is getting mature. By LOCOS technique, reliable, effective and low-cost device isolation structures can be obtained. However, the conventional LOCOS technique suffers from the problems of stress and bird's effect at the surroundings of the isolation structures. The formation of bird's effect, especially, causes ineffective isolation for a small size device. Therefore, a shallow trench isolation structure (STI) is necessarily applied in high-density devices instead of using LOCOS techniques.
The conventional shallow trench isolation technique uses silicon nitride as a hard mask. Sharp trenches are then defined on the semiconductor substrate by anisotropic etching. Then, silicon oxide is filled in the trenches to form isolation structures.
FIG. 1A to FIG. 1C are the cross-section views showing a conventional process of fabricating a shallow trench isolation structure. Referring first to FIG. 1A, on a substrate 100, a pad oxide layer 102 is formed to protect the substrate surface. Then, a silicon nitride layer 104 is formed by chemical vapor deposition (CVD). Next, on the silicon nitride layer 104, a patterned photoresist layer 105 is formed to define the trench.
Next, referring to FIG. 1B, using the photoresist layer 105 as an etching mask, the silicon nitride layer 104, pas oxide layer 102 and the substrate 100 are etched to form the trench 106 and the trench 108. The photoresist layer 105 is then removed.
Next, referring to FIG. 1C, on the substrate 100, a silicon oxide layer 110 is formed to cover the silicon nitride layer 104 and to fill the trench 106 and the trench 108. The silicon oxide layer 110 can be, for example, a TEOS oxide layer formed by atmospheric pressure chemical vapor deposition (APCVD), using tetra-ethyl-ortho-silicate (TEOS) as gas source.
Next, referring to FIG. 1D, the silicon oxide layer 110 on the silicon nitride layer 104 is removed by chemical mechanical polishing (CMP) so that silicon oxide 114 and silicon oxide 116 are left in the trench 106.
Then, referring to FIG. 1E, the silicon nitride layer 104 is first removed by hot phosphoric acid. Through hydrofluoric acid soaking, the pad oxide layer 102 is removed to form isolation region 114a and isolation region 116a.
However, the above-mentioned shallow trench isolation technique has a few problems as applied in high integration IC. During the process of polishing the TEOS oxide layer 110 by CMP, particles in the slurry makes the surfaces of the oxide layer 114 and the oxide layer 116 form a lot of scratches 140, as shown in FIG. 1D. Further, during the subsequent process of hydrofluoric acid soaking, the scratches 140 are eroded to form microcrack 140a. Referring to FIG. 1E, if scratches 140 are formed on the oxide layer 110 in the small trench 116 during polishing, after the hydrofluoric acid soaking, the conductive layers formed on the two sides of the isolation regions 116a will suffer from the problem of bridging.
Using CMP also has another problem. Over-polishing is necessary to completely polish away the silicon oxide layer 110 on the silicon nitride layer 104. However, over-polishing has a great effect on the wider trench 106. Over-polishing causes the formation of concave in the wider trench, which is so-called "dishing effect".